This application claims the benefit of Korean Application No. 7178/1999 filed Mar. 4, 1999, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a high voltage device and a method for fabricating the same, in which a diode is used for reducing the influence of an electric field to silicon for enabling a higher operative voltage without an increased thickness of silicon on an upper portion thereof.
2. Background of the Related Art
In general, a power MOSFET has an excellent switching speed compared to other semiconductor devices. Also, because it has a comparatively low withstand voltage (below 300V), it has a low turn-on resistance. Accordingly, a high voltage lateral power MOSFET is frequently used as a power device for a high density device packing. Among high voltage power devices, there are, among others, DMOSFET (Double-diffused MOSFET), IGBT (Insulated Gate Bipolar Transistor), EDMOSFET (Extended Drain MOSFET) and LDMOSFET (Lateral Double-diffused MOSFET). Though the LDMOSFET has a variety of applications in chips, such as an HSD (High Side Driver), LSD (Low Side Driver) and an H-bridge circuit and can be fabricated easily, the LDMOSFET has disadvantages in that it has a high threshold voltage, and a breakdown can occur at the surface of a silicon substrate in a drift region near a channel because the doping concentration in the channel region of the LDMOSFET is not uniform.
A high voltage transistor developed recently to avoid the problems of earlier devices is an EDMOSFET. In general, because the maximum electric field intensity in a high voltage device, which increases as the operative voltage increases, limits operation characteristics of the device, the silicon should be thick. The thicker the silicon, the more difficult it is to provide dielectric isolation between devices. Presently, the technology for integrating high voltage devices and low voltage devices into one semiconductor chip is widely applied, according to which the technique of dielectric isolation between devices using an SOI (Silicon On Insulator) wafer is frequently used.
A related art high voltage device will be explained with reference to the attached drawings. FIG. 1 illustrates a section of the related art high voltage device.
As shown in FIG. 1, the related art high voltage device is provided with a first conduction type substrate 11, a buried oxide film 12 formed on the substrate 11, and a first conduction type semiconductor layer 13 formed on the buried oxide film 12. A second conduction type drift region 14 is formed in the semiconductor layer 13, and a second conduction type well region 15 is formed in the second conduction type drift region 14. A collector impurity region 16 is formed in the second conduction type well 15 region. A first conduction type drift region 17 is formed in the semiconductor layer 13 spaced from the second conduction type drift region 14. A first conduction type well region 18 is formed in the first conduction type drift region 17, an emitter impurity region 19 is formed in the first conduction type drift region 17, and a first insulating layer 20 is formed on the second conduction type drift region and extends to one side of the emitter impurity region 19. A second insulating layer 21 is formed on the first conduction type drift region 14 between the collector impurity region 16 and the second conduction type drift region 17. A gate electrode 22 is formed on the first insulating layer 20 and extends to overlap a portion of the second insulating layer 21. A third insulating layer 23 is formed on the second insulating layer 21 and the gate electrode 22. An emitter electrode 19a, insulated from the gate electrode 22 by the third insulating layer 23, is electrically connected to the emitter impurity region 19. A collector electrode 16a is electrically connected to the collector impurity region 16, and a field plate region 24 is formed to overlap with the gate electrode 22 with the third insulating layer 23 disposed therebetween. The field plate electrode 24 is formed to disperse an electric field formed in the second conduction type drift region 17 during operation to obtain a high breakdown voltage. Upon application of the operative voltage to the collector electrode 16a, the first conduction type drift region 14 is brought into a saturated depletion state to move electrons through the collector impurity region 16.
While the related art high voltage device is operative as a power device, an equipotential is applied both to the gate electrode 22 and the field plate electrode 24, so that the depletion region in the second conduction type drift region 17 disperses an electric field concentrated on an edge portion of the gate electrode 22. This is done to prevent a breakdown occurrence at the edge portion of the gate electrode.
The thickness of the silicon layer having the high voltage device formed thereon in the aforementioned SOI wafer is determined according to a range of the high voltage, which can be expressed as follows.                     V        =                              (                                                            t                  s                                2                            +                              3                ⁢                                  t                  ox                                                      )                    ⁢                      E            y                                              (        1        )            
Where, V is the breakdown voltage, ts is the thickness of silicon, tox is the thickness of the buried oxide film, and Ey is a critical electric field of the silicon in a vertical direction.
FIG. 2 illustrates a voltage distribution of the related art high voltage device, wherefrom it can be understood that equipotential planes exist in the vertical direction as well as in a horizontal direction in an upper silicon layer. Furthermore, there are equipotential planes in a horizontal direction under the collector electrode, implying the presence of a vertical electric field therein.
FIG. 3 illustrates the electric field under the collector electrode in the related art device. It can be understood that there is an electric field, not in the horizontal direction, but in the vertical direction, and that there are horizontal equipotential planes under the collector electrode. The vertical electric field shows a maximum in the vicinity of a junction between a P-conduction type upper silicon layer and an N-conduction type drift region. This means that the depletion layer is formed and an electric field is centered on the junction when a voltage is started to be applied to the collector electrode. Therefore, though the depletion layer becomes wider and the electric field becomes larger as the voltage to the collector electrode becomes higher, the position of the maximum electric field shows no change.
FIG. 4 illustrates voltage vs. current of the collector when a voltage is applied to the gate electrode in the related art high voltage device. The measurements are obtained as a result of observation of the collector current as the collector voltage is increased after the application of a voltage to the gate electrode.
The related art high voltage device has the following problems. As can be known from equation (1), the higher the breakdown voltage, the thicker the silicon layer in the wafer must be. The thicker silicon layer requires a deeper trench for the dielectric isolation technique, which is not possible to form in an actual process. In order not to form the thicker silicon layer in the fabrication of the high voltage device, either the thickness of the oxide film must be increased or a critical electric field on the silicon layer must be made larger. However, increasing the thickness of the buried oxide film causes deflection of the wafer due to material properties of the oxide film and the silicon layer. T his causes poor fabrication of the device.
Accordingly, the present invention is directed to a high voltage device and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a high voltage device and a method for fabricating the same, in which the influence of an electric field on a silicon layer is reduced for increasing an operative voltage of the high voltage device without increasing the thickness of the silicon layer.
Additional features and advantages of the present invention will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a high voltage device includes: a semiconductor substrate; a first semiconductor layer formed between an underlying first insulating layer and an overlying second insulating layer buried within the semiconductor substrate; first and second drift regions formed over the second insulating layer in the semiconductor substrate and spaced apart from each other; an emitter impurity region formed in the first drift region; a collector impurity region formed in the second drift region; a second semiconductor layer adjacent to and insulated from the collector impurity region, and connected to the first semiconductor layer; a third semiconductor layer adjacent to and insulated from the emitter impurity region, and connected to the first semiconductor layer; a gate electrode formed over and insulated from the first drift region adjacent to the emitter impurity region; an emitter electrode electrically connected to the emitter impurity region and the third semiconductor layer, the emitter electrode being insulated from the gate electrode; a collector electrode electrically connected to the collector impurity region and the second semiconductor layer; and, a field plate electrode formed between the collector electrode and the emitter electrode, and insulated from the gate electrode.
In another aspect of the present invention, a high voltage device includes: a semiconductor substrate; a first semiconductor layer formed between an underlying first insulating layer and an overlying second insulating layer buried within the semiconductor substrate; a third insulating layer surrounding a device isolation region above the second insulating layer in the semiconductor substrate; a first impurity region formed in the device isolation region; a second impurity region formed in the device isolation region and spaced apart from the first impurity region; a second semiconductor layer outside the device isolation region and connected to the first semiconductor layer; a third semiconductor layer outside the device isolation region and connected to the first semiconductor layer; a gate electrode over and insulated from the device isolation region and adjacent to the first impurity region; a fourth insulating layer over the gate electrode and the device isolation region; a first electrode electrically connected to the first impurity region and the third semiconductor layer; and, a second electrode electrically connected to the second impurity region and the second semiconductor layer.
In yet another aspect of the present invention, a method for fabricating a high voltage device includes: (1) forming a first insulating layer in a first conduction type substrate, a second conduction type first semiconductor layer on the first insulating layer, and a second insulating layer on the second conduction type first semiconductor layer; (2) dividing a portion of the substrate above the second insulating layer into first and second conduction type drift regions; (3) selectively removing the first and second conduction type drift regions and surrounding the remaining portions of the first and second conduction type drift regions with a third insulating layer to form a device isolation region; (4) forming a second conduction type second semiconductor layer and a first conduction type third semiconductor layer outside the device isolation region and each connected to the second conduction type first semiconductor layer; (5) forming an emitter impurity region in the first conduction type drift region and a collector impurity region in the second conduction type drift region in the device isolation region; (6) forming a gate electrode over the first conduction type drift region adjacent to the emitter impurity region; and, (7) forming an emitter electrode, a collector electrode, and a field plate electrode, each being insulated from the gate electrode, wherein the emitter electrode is connected to the emitter impurity region and the first conduction type third semiconductor layer, the collector electrode is connected to the collector impurity region and the second conduction type second semiconductor layer, and the field plate electrode is disposed between the emitter electrode and the collector electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.